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Posters & Diagrams

Posters from previous presentations, as well as diagrams of SHIRA.

FPGA

Smart Processor Extensions

FPGA

Hardware Accelerators

FPGA

Trigonometric Function Approximation

FPGA

SHIRA High Level Flow

FPGA

SHIRA Detailed Flow

SHIRA


The Software/Hardware Implementation Research Application (SHIRA) tool chain is being designed to allow programmers to code their applications as they normally would (in a sequential manner). From there it is designed to automatically parallelize the code so that is may be run on a multiprocessor system-on-chip (MPSoC)

Below are several of the papers written in the course of developing SHIRA. They are organized from highest to lowest (from software, through compilation, to hardware).

Funding & Support

CARG is funded in part by a Natural Sciences and Engineering Research Council of Canada (NSERC) strategic grant.

Modular Design of Configurable/Reconfigurable systems", 2008-2010, PI: Miodrag Bolic, Co-investigators: Voicu Groza.

Both Altera and Larus Technologies have been integral industry partners.


»Pre-Compilation Level

This level deals with the User Interface, as well as the high level software code parallelization that occurs before the C code is compiled into assembly.

»Compilation Level

The compilation level deals with the COINS compiler, as well as the Instruction Set Extension Identification and Co-Processor Generation projects.

»Post Compilation Level

The post compilation section is a smaller portion of SHIRA that deals with the conversion of the assembly output from COINS into the Memory Initialization File format. These files will be used at the hardware level to initialize the memory blocks on the FPGAs.

»Hardware Level

The hardware level ties all the features together in the Simulator and Interconnection Network Generator (SING). The goal is to have the parallelized and customized software run on the customized hardware for maximum speedup.